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high speed data communication across multidrop wireless subsystem
by subbash on Mar 29, 2010 |
subbash
Posts: 2 Joined: Mar 4, 2010 Last seen: May 5, 2010 |
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I am, working on a final year B.E project called 'HIGH SPEED DATA COMMUNICATION ACROSS MULTIDROP WIRED/WIRELESS SYSTEM" here we are supposed to send both data and clock together as its shown in the ppt and v need to transmit it and then recieve at the receiver end and decode it so sir, can i use your code which is posted at open cores.org......... I have attached the codes which has been posted........ It would be of great help if you would let me know if i can use it in my project......
code for transmiter:
//-----------------------------------------------------------------------------
// Title : Test Circuit for Manchester Code Transmitter
// Project : ECE 491 - Senior Design 1
//-----------------------------------------------------------------------------
// File : mxtest.v
// Author : John Nestor
// Created : 21.10.2004
// Last modified : 21.10.2004
//-----------------------------------------------------------------------------
// Description :
// This module is intended to exercise the Manchester transmitter designed for Lab 5.
// To use this module, instantiate it with input connections that specify the number
// of bytes to be transmitted (1-4) on the nbytes input and up to 4 data bytes to
// be transmitted connected to inputs d0-d3. Start out connecting these inputs
// to constants, but later you may want to connect the switches to one of the data inputs.
//
// Connect "run" to a pushbutton input.
// When run=1, this module will send the data bytes to the parallel interface of
// the transmitter and then wait several clock cycles and the retransmit the same
// values as long as run is asserted.
//-----------------------------------------------------------------------------
// Modification history :
// 21.10.2004 : created
module mxtest(clk, reset, run, byte_limit, d0, d1, d2, d3, start, data, ready);
input clk;
input reset;
input run;
input [1:0] byte_limit;
input [7:0] d0, d1, d2, d3;
output start;
output [7:0] data;
input ready;
reg [7:0] data;
reg start;
parameter WAIT_TIME = 31;
parameter WAIT_BITS = 5;
//-----------------------------------------------------------------------------
// byte counter
//-----------------------------------------------------------------------------
reg byte_count_enable;
reg [1:0] byte_count;
reg byte_count_reset;
always @(posedge clk)
if (reset | byte_count_reset) byte_count
Titletx.doc (36 kb)
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